1. Field of the Invention
The present invention relates generally to integrated circuit devices, and more particularly to integrated circuit device fabrication.
2. Description of the Background Art
Integrated circuit (IC) devices are generally fabricated on a substrate, such as a semiconductor wafer. The wafer is subjected to various fabrication processing steps to form dopant regions, dielectric layers, metal layers with metal lines, vias providing electrical connection between metal lines on different levels, trenches, and other regions and structures. The fabrication processing steps are generally well known and may include diffusion, implantation, deposition, electroplating, chemical-mechanical polishing (CMP), annealing, lithography, and etching, for example. The fabrication processing steps result in an integrated circuit device formed in one or more levels of the wafer. Several integrated circuit devices are typically formed on a single wafer. The integrated circuit devices are tested at different steps in the fabrication process to insure that they operate as designed. The tests allow for identification of defective devices so that they may be separated from good devices. The yield of a fabrication process is a measure of the number of good structures, self-contained devices, or regions relative to defective ones fabricated using the process.
Various process control mechanisms may be employed to monitor and control each step in the fabrication process. However, due to the complexity of fabrication processes and the large number of process parameters involved in each processing step, it is relatively difficult to monitor and control a processing step. Embodiments of the present invention allow for identification of process parameters that appreciably affect yield, resulting in a manageable number of process parameters that may be monitored and optimized to increase yield, improve device performance, or both.